1. Field of the Invention
The present invention relates to random access memory (RAM). More specifically, it relates to a pipelined dual port RAM for use in a "color palette" to display a plurality of colors on an analog color monitor.
2. Description of the Prior Art
Referring to FIG. 5, a block diagram of a known color palette circuit is shown. A central processing unit (CPU) A sends address, data and control signals to a video controller B, which formats the information from CPU A, and stores the formatted information in video RAM C. Each pixel of the image to be displayed is represented by 8 bits, which are transmitted to Random Access Memory Digital-to-Analog Converter (RAMDAC) D. The RAMDAC is composed of a random access memory and a digital-to-analog converter. The random access memory, also known as a color palette, in the RAMDAC receives the 8 bit signal representing a pixel from video RAM C and converts the 8 bit signal into an 18-bit signal, each 6 bits of which stands for a respective red, green or blue (R,G,B) signal. The 6 bits of color signal allow for 64 levels of color for each one of the R,G,B signals, resulting in a total of 64.sup.3 or 256K different colors. The monitor can display 256 different colors at any given instant. The 18 bit signals are converted into analog signals by means of the digital-to-analog converter in RAMDAC D and are fed to analog monitor E. An extremely stable and precise clock is needed for the aforesaid technique. In the known art, a phase locked loop (PLL) has been used to generate the clock pulses. However, this approach is complicated and expensive.